The performance of digital systems is heavily dependent on the frequency. On the other hand, the higher the frequency, the shorter is the time remaining to convey digital signals reliably from a driver via a conductor track to the receivers. Limiting factors are the clock-to-output time, the run time on the board, the setup/hold time of the receiver, output and input skew (skew of the transmitters and receivers) and clock skew or jitter (tskew).
FIG. 1 shows the timing of a digital signal at the output of the driver of a transmitter and at the input of the receiver, the diagram illustrating the time effect of the factors mentioned.
The setup time requirement determines for how many ns before the clock edge a signal to be clocked in has to be stable. The hold time requirement determines for how long after a clock edge the signal has to remain stable. Thus, if the position of the times of clock and signal with respect to each other is varied, this has a positive effect in respect of one requirement, but a negative effect in respect of the other requirement.
In extremely favorable environmental conditions (low temperature, high supply voltage, powerful drivers, receiver with small parasitic capacity) the signals are very fast. In this case a hold time problem arises.
In extremely unfavorable environmental conditions (high temperature, low supply voltage, weak drivers, receiver with large parasitic capacity) the signals are very slow. However, the clock may not also be slow. In this case a setup time problem arises.
The run time of clock and signals must be optimized in such a way that even in extreme environmental conditions no timing violations arise anywhere. The tradeoff determines the maximum possible frequency and therefore the performance of the system or imposes constraints in the architecture.
Typically, a table is produced which lists all the timing parameters to be taken into account for each signal and calculates a budget or a violation. This is performed for the fast and the slow case. The parameters can be influenced (within limits) via the choice of components, the board layout and (if transmitter or receiver are contained in an ASIC) via the ASIC design. The limits result from the components chosen (driver strength, setup/hold time according to the data sheet), the distances between the components on the board, the architecture of the networks (unidirectional/bidirectional signals, number of drivers/receivers involved) and frequency or clock period. Then an optimization is performed. However, if the optimization is performed for the slow case, this is detrimental to the fast case, and vice versa.
TABLE 1Setup and hold time margin calculationsignaltskewtco,tco,trun,trun,tsetuptholdholdsetupnamechipminmaxminmaxmarginmar-ginhold margin = tco, min + trun, min − tskew - thold setup margin = 7.5 ns - tco, max - trun, max − tsetup - tskew 
In some cases the problem was also not even solved at all, but worked around. An example is SDRAM address signals in the PC: In this case the address signals are sent off from the driver and clocked in at the receiver only with the next-but-one clock. This has implications for the design of the SDRAM controller and the performance of the overall system. Moreover, PC motherboards running at an SDRAM bus frequency of 133 MHz are now only equipped with a maximum of 3 SDRAM modules (DIMMs) in order to steer clear of timing problems. However, this limits the maximum possible memory configuration.
An already partly common variant for minimizing the clock skew between transmitter and receiver uses a PLL in the transmitter device (e.g. ASIC); see FIG. 2. In this arrangement, clock and signals for the SDRAMs come from the same chip. An additional clock output is looped back again to the PLL of the transmitter and in fact has the same physical length as the receiver clock. The PLL transmits this feedback clock earlier in line with the board run time t_run so that in this way the feedback clock will then arrive in phase with the reference clock clk_ref at the PLL input of the ASIC. Because the receiver clock has the same run time, the receiver clock is also automatically in phase at its receiver at time T0. The clock skew between transmitter and receiver is therefore always equal to zero.